The present invention generally relates to improved methods of making flash memory devices such as EEPROMs. More particularly, the present invention relates to non-volatile flash memory devices with non-uniform channel doping having reduced short channel effects.
Semiconductor devices typically include multiple individual components formed on or within a substrate. Such devices often comprise a high density section and a low density section. For example, as illustrated in prior art FIG. 1a, a memory device such as a flash memory 10 comprises one or more high density core regions 11 and a low density peripheral portion 12 on a single substrate 13. The high density core regions 11 typically consist of at least one Mxc3x97N array of individually addressable, substantially identical floating-gate type memory cells and the low density peripheral portion 12 typically includes input/output (I/O) circuitry and circuitry for selectively addressing the individual cells (such as decoders for connecting the source, gate and drain of selected cells to predetermined voltages or impedances to effect designated operations of the cell such as programming, reading or erasing).
Prior art FIG. 1b represents a fragmentary cross section diagram of a typical memory cell 14 in the core region 11 of prior art FIG. 1a. Such a cell 14 typically includes the source 14b, the drain 14a and a channel 15 in a substrate or P-well 16; and the stacked gate structure 14c overlying the channel 15. The stacked gate 14c further includes a thin gate dielectric layer 17a (commonly referred to as the tunnel oxide) formed on the surface of the P-well 16. The stacked gate 14c also includes a polysilicon floating gate 17b which overlies the tunnel oxide 17a and an interpoly dielectric layer 17c overlies the floating gate 17b. The interpoly dielectric layer 17c is often a multilayer insulator such as an oxide-nitride-oxide (ONO) layer having two oxide layers sandwiching a nitride layer. Lastly, a polysilicon control gate 17d overlies the interpoly dielectric layer 17c. Each stacked gate 14c is coupled to a word line (WL0, WL1, . . . , WLn) while each drain of the drain select transistors are coupled to a bit line (BL0, BL1, . . . , BLn). The channel 15 of the cell 14 conducts current between the source 14b and the drain 14a in accordance with an electric field developed in the channel 15 by the stacked gate structure 14c. Using peripheral decoder and control circuitry, each memory cell 14 can be addressed for programming, reading or erasing functions.
In the semiconductor industry, there is a continuing trend toward higher device densities to increase circuit speed and packing densities. To achieve these high densities there has been and continues to be efforts toward scaling down the device dimensions on semiconductor wafers. Scaling in this sense refers to proportionately shrinking device structures and circuit dimensions to produce a smaller device that functions according to the parameters as a larger unscaled device. In order to accomplish such scaling, smaller and smaller features sizes are required. This includes the width and spacing of features including gate length.
The requirement of small features raises numerous concerns associated with flash memory devices, especially with regard to consistent performance and reliability. For example, as feature size decreases, such as a decrease in gate length, variations in size (such as gate length) increase. That is, it is difficult to maintain critical dimension control as the size decreases. As gate length decreases, the possibility of short channel effects increases. Nitrided tunnel oxide layers in some instances also contribute to increases in short channel effects.
A short channel effect occurs as the length between the source and drain is reduced. Short channel effects include Vt rolloff (Vt is the threshold voltage), drain induced barrier lowering (DIBL), and excess column leakage. DIBL is often caused by the application of drain voltage in short channel devices. In other words, the drain voltage causes the surface potential to be lowered.
In view of the aforementioned concerns and problems, there is an unmet need for making flash memory cells of improved quality with increased integration, and especially for sub 0.18 xcexcm flash memory cells having reduced short channel effects.
As a result of the present invention, non-volatile flash memory device fabrication is improved thereby producing devices having improved reliability. By employing the methods of the present invention which provide for non-uniform channel doping, the formation of a flash memory device on the sub 0.18 xcexcm scale having reduced short channel effects is facilitated. Specifically, the present invention enable further scaling of non-volatile flash memory devices while minimizing and/or eliminating undesirable short channel effects, including at least one of Vt rolloff, high DIBL, excess column leakage, and variations in gate length across the product array. Undesirable short channel effects caused by the use of nitrided tunnel oxide layers are also minimized.
One aspect of the present invention relates to a method of making a flash memory cell involving the steps of providing a substrate having a flash memory cell thereon; forming a self-aligned source mask over the substrate, the self aligned source mask having openings corresponding to source lines; implanting a source dopant of a first type in the substrate through the openings in the self-aligned source mask corresponding to source lines; removing the self-aligned source mask from the substrate; cleaning the substrate; and implanting a medium dosage drain implant of a second type to form a source region and a drain region in the substrate adjacent the flash memory cell.
Another aspect of the present invention relates to a method of making a flash memory cell involving the steps of providing a substrate having a flash memory cell thereon; heating the substrate in an atmosphere containing oxygen and optionally at least one inert gas; forming a self-aligned source mask over the substrate, the self aligned source mask having openings corresponding to source lines; implanting a source dopant of a first type in the substrate through the openings in the self-aligned source mask corresponding to source lines; removing the self-aligned source mask from the substrate; cleaning the substrate; heating the substrate; and implanting a medium dosage drain implant of a second type to form a source region and a drain region in the substrate adjacent the flash memory cell.
Yet another aspect of the present invention relates to a method of making a flash memory cell involving the steps of providing a substrate having a flash memory cell thereon; forming a self-aligned source mask over the substrate, the self aligned source mask having openings corresponding to source lines; implanting a source dopant of a first type in the substrate through the openings in the self-aligned source mask corresponding to source lines; removing the self-aligned source mask from the substrate; cleaning the substrate; heating the substrate in an atmosphere containing oxygen and optionally at least one inert gas; and implanting a medium dosage drain implant of a second type to form a source region and a drain region in the substrate adjacent the flash memory cell.